1. Field of the Invention
The present invention relates to a liquid crystal display device (LCD), and more particularly, to an in-plane-switching (IPS) mode LCD and a manufacturing method thereof.
2. Description of the Related Art
Cathode ray tubes (CRTs) have been most widely used for display devices to display image information on a screen. However, the CRTs are large and heavy in their volume and weight for their display region and so there has been much inconvenience in an aspect of use.
With the recent development of the electronic industry, display devices whose usage has been limited to a television (TV) braun tube are now widely used for personal computers (PCs), notebook computers, automobile instrument panels, and electronic display boards. With development of information and telecommunication technology, next-generation display devices that are capable of processing and realizing large-capacity image information is emerging as an important issue.
The next-generation display devices should be lightweight, slim in profile, have high brightness, a large screen, low power consumption, and a low price. As one of the next-generation display devices, LCDs are drawing attention.
The display resolution in LCDs is excellent compared to other display devices and a response time is as fast as CRTs when displaying moving images.
The types of LCDs primarily being used are twisted nematic (TN) mode LCDs. In TN mode LCDs, electrodes are installed on two substrates, respectively, a director of liquid crystal molecules is arranged so as to be twisted 90 degrees, and then a voltage is applied to the respective electrodes so that the director of the liquid crystal molecules is driven.
However, the TN mode LCD has a crucial disadvantage of a narrow viewing angle.
To solve the narrow viewing angle problem, studies on LCDs adopting a variety of new modes are actively in progress. Examples of such modes includes an IPS mode and an optically compensated birefringence (OCB) mode.
The IPS mode LCDs have two electrodes formed on the same substrate so as to drive the liquid crystal molecules with the molecules maintained parallel with respect to the substrate, applies a voltage between the two electrodes to generate a horizontal, transverse electric field with respect to the substrate. That is, a longitudinal axis of the liquid crystal molecules is not allowed to stand up with respect to the substrate.
Therefore, the IPS mode LCDs have a small variation in a birefringence of the liquid crystal molecules with respect to a vision direction, and thus have far better viewing angle characteristics compared to the TN mode LCDs of a related art.
A structure of the IPS mode LCDs of the related art will be described below with reference to the accompanying drawings.
FIG. 1 is a schematic, plan view of the IPS mode LCDs of the related art and FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1.
As illustrated in FIGS. 1 and 2, IPS mode LCDs include: a plurality of gate lines 112 horizontally arranged in parallel with each other, and spaced a predetermined interval on a substrate 110; a plurality of common lines 116 horizontally arranged in parallel with each other, closely to the gate lines 112; and a plurality of data lines 124 crossing with the gate line 112 and common line 116 and vertically arranged and spaced a predetermined interval, for defining a pixel region P together with the gate lines 112.
A thin film transistor (TFT) T that includes a gate electrode 114, semiconductor layers (not shown), a source electrode 126, and a drain electrode 128 are formed at crossings of the gate lines 112 and the data lines 124. The source electrode 126 is connected with the data line 124 and the gate electrode 114 is connected with the gate line 112.
A gate pad 152 is formed at one end of the gate lines 112. On the gate pad 152, a gate pad upper electrode 153 is connected with the gate pad 152 through a contact hole 155 that passes through a gate insulation layer 118 and a passivation layer 134.
A pixel electrode 130 connected with the drain electrode 128 and a common electrode 117 arranged in parallel with the pixel electrode 130 and connected with the common lines 116 are formed on an upper part of the pixel region P.
The pixel electrode 130 includes: a plurality of vertical parts 130b extended from the drain electrode 128, formed in parallel with the data lines 124, and spaced a predetermined interval each other; and a horizontal part 130a for incorporating the vertical parts 130b into one part at an upper portion of the common lines 116.
The common electrode 117 includes: a plurality of vertical parts 117b vertically extended from the common lines 116 and alternately formed in parallel with the vertical parts 130b of the pixel electrode 130; and a horizontal part 117a for incorporating the vertical parts 117b into one part.
The horizontal part 130a of the pixel electrode 130 is formed with the gate insulation layer 118 interposed on part of the common lines 116 and forms a storage capacitor C together with the common lines 116.
The common lines 116 and the common electrode 117 are made of the same material as the gate lines 112 and formed on the same layer as the gate lines 112.
The gate lines 112 and the data lines 124 have, at their one end, an input pad for applying scanning signals and data signals provided from an external printed circuit board (PCB) to the gate lines 112 and the data lines 124.
The common lines 116 arranged in parallel with the gate lines 112 are connected with a common-voltage supply line 159 provided to an outer block of a panel.
Since the common-voltage supply line 159 is formed in a direction that crosses the gate lines 112 so as to incorporate the common lines 116 into one line, the common-voltage supply line 159 is made of the same material as the data lines 124 and formed on the same layer as the data lines 124 so as to avoid connection of the gate lines 112 and the common-voltage supply line 159 on the same plane.
Therefore, since the common-voltage supply line 159 made of the same material as the data lines 124 has the gate insulation layer 118 interposed on a space between the common-voltage supply line 159 and the common lines 116, a contact hole 165b is formed in the common lines 116 and another contact hole 165a is formed in the common-voltage supply line 159 so that the common lines 116 are connected with the common-voltage supply line 159 by a jumping electrode 166.
With this configuration, in case the common lines 116 and the common-voltage supply line 159 are formed using different material and connected using the jumping electrode 166 as described above, common signals pass through PCB-> TCP (tape carrier package)-> a common-voltage supply line (data line material)->a jumping electrode and is finally applied to the common lines (gate line material).
In that case, a resistance of the data line material is larger than that of the gate line material. Further, in the case that a contact area for the common lines is made large so as to secure a contact area for the jumping electrode 166, a contact resistance is increased. Thus, a contact resistance for an external TCP is increased and common signals applied from the outside are delayed. Signal delay due to the large contact resistance between the common lines and the jumping electrode causes image quality deterioration.